Main Article Content
High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).
These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.
Authors retain the copyright without restrictions for their published content in this journal. IJSRTM is a SHERPA ROMEO Journal.
- A. Calimera, E. Macii, and M. Poncino,(2012) “Design techniqures for NBTItolerant power-gating architecture,” IEEE Trans. Circuits Syst., Exp. Briefs, vol. 59, no. 4, pp. 249–253.
- Cui, x.; Liu, W.; Chen, X.; Swartzlander, E.; Lombardi, F.,(2015) “A Modified Partial Product Generator for Redundant Binary Multipliers,” in Computers, IEEE Transactions on ,vol.PP, no.99, pp.11
- IChyn Wey; ChienChang Peng; FengYu Liao,(2015) "Reliable Low Power Multiplier Design Using Fixed Width Replica Redundancy Block," in Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.23, no.1, pp.7887
- Ing-Chao Lin, Yu-Hung Cho, Yi-Ming Yang.(2014) “Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS.
- Jiang, H.; Han, J.; Qiao, F.; Lombardi, F.,(2015) "Approximate Radix8 Booth Multipliers for Low Power and High performance Operation," in Computers, IEEE Transactions on , vol.PP, no.99, pp.11
- Jiun-Ping Wang, Shiann-Rong Kuang, and Shish-Chang Liang.,(2011) “High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 1.
- More, T.V.; Kshirsagar, R.V.,(2011) "Design of low power column bypass multiplier using FPGA," in Electronics Computer Technology (ICECT), 2011 3rd International Conference on , vol.3, no., pp.431435, 810.
- Prabhu, A.S.; Elakya, V.,(2012) "Design of modified low power booth multiplier," in Computing, Communication and Applications (ICCCA), 2012 International Conference on , vol., no., pp.16, 2224.
- Rajput, R.P.; Swamy, M.N.S.,(2012) "High Speed Modified Booth Encoder Multiplier for Signed and Unsigned Numbers," in Computer Modelling and Simulation (UKSim), 2012 UKSim 14th International Conference on , vol., no., pp.649654, 2830.
- Srinivas, K.B.; Aneesh, Y.M.,(2014) "Low power and high speed row and column bypass multiplier," in Computational Intelligence and Computing Research (ICCIC), 2014 IEEE International Conference on , vol., no., pp.14, 1820.
- Surendran, E.K.L.; Antony, P.R.,(2014) "Implementation of fast multiplier using modified Radix4 booth algorithm with redundant binary adder for low energy applications," in Computational Systems and Communications (ICCSC), 2014 First International Conference on , vol., no., pp.266271, 1718.
- H.-I. Yang, S.-C. Yang, W. Hwang, and C.-T. Chuang,(2011) “Impacts of NBTI/PBTI on timing control circuits and degradation tolerant design in nanoscale CMOS SRAM,” IEEE Trans. Circuit Syst., vol. 58, no. 6, pp. 1239–1251.
- Yongho Lee, Taewhan Kim,(2011) “A Fine-Grained Technique of NBTI-Aware Voltage Scaling and Body Biasing for Standard Cell Based Designs” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS.
- Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, and Malgorzata Marek-Sadowska,(2011) “Performance Optimization Using Variable-Latency Design Style” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 10.
- Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, and Kaushik Roy,(2010) “Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 11.